vllm.models.muse_spark.nvidia.specialized_decode.cutedsl.moe.routing
¶
Muse Spark routing for decode batches of at most 8 tokens: sigmoid of the FP32 router logits plus the correction bias, top-8 of 256 experts, the selected sigmoid scores renormalized and scaled. Writes the global expert ids (int32 [b, 8]) and the routing weights (FP32 [b, 8]) that the routed MoE op takes.
The result is bitwise equal to fused_musespark1x_routing
(vllm/models/muse_spark/common/ops/fused_routing.py: on CUDA the
muse_spark_routing op, written to match its Triton _routing_kernel bit
for bit) as Muse Spark calls it:
sigmoid scores, no output multiplier (it is folded into the router weight after
loading) and router_score_division_eps = 1e-15. With renormalize the weights
are score * (scale / (sum + 1e-15)), the sum taken in top-k order from 0.0;
without it they are score * scale.
Optionally the same launch also writes the TRT-LLM-gen routing metadata of this
rank's experts for one GEMM tile, as FlashInfer's routingIndicesDynBlockKernel
(the routed MoE op's own routing kernel) writes it, so the routed MoE GEMMs need no
routing kernel of their own: local expert e takes ceil(count_e / tile) CTAs at
the exclusive prefix sum of the CTA counts in expert order, and its routes take
the permuted rows from that CTA offset times tile, in token order. A route to
another rank's expert and the padding rows of each expert's last CTA map to -1.
The histogram and per-expert token counts are not written, nor is any element
past what these fields take (metadata_size leaves a guard element).
Launch: one CTA of 256 threads, one warp per token row, with programmatic
dependent launch: the bias (a weight) is read before griddepcontrol.wait,
the logits after it; the dependents launch at the grid's end. Without metadata
the warps past the last token row exit at once.
Selection: lane l holds experts 8l .. 8l + 7 and sorts them once by a key that orders as score + bias (NaN is outside the domain; -0.0 keys as +0.0). Each of the 8 rounds takes the warp maximum of the lanes' head keys and the lowest lane holding it, matching the Triton argmax (the lowest expert among equal values); the winner pops its head.
Arithmetic: every float operation is the PTX instruction Triton emits for the
same expression of _routing_kernel (primitives.sigmoid_f32,
add_rn, mul_rn, div_full_f32), as inline assembly, so the compiler
can neither contract nor reorder them.
Functions:
-
compile_routing–cute.compilethe routing kernel of one variant, with these extra -
compiled_routing–compile_routingof one variant, once per process (before CUDA graph -
metadata_size–int32 elements of the metadata for GEMM tile
tile_n: the fields -
prepare–Compile the variants
routetakes with and without metadata (before -
route–ids[b, 8] (global expert ids) andweights[b, 8] of the top-8
_RoutingKernel
¶
The routing of up to 8 token rows; metadata and renormalize
are compile-time.
Methods:
-
route_row–Warp
warp: the top-8 of logits rowwarpinto its ids and -
write_expert_metadata–Thread e (e < num_local): local expert e's CTAs (batch index and
-
write_route_metadata–Thread r (r < 8 b): route r's permuted row, or -1 for another
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
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route_row(logits, bias_row, ids, weights, scale, warp, lane)
¶
Warp warp: the top-8 of logits row warp into its ids and
weights rows; lanes 0..7 return the global id of pick lane.
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
write_expert_metadata(meta, tokens, cta_offset, warp_ctas, num_local, tile, expert, warp, lane)
¶
Thread e (e < num_local): local expert e's CTAs (batch index and row limit) and its permuted rows (token ids in token order, then -1 to the end of its last CTA); thread 0 the padded size and CTA count. Every thread of the block calls it (it holds a barrier).
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
write_route_metadata(meta, tokens, cta_offset, routes, local_offset, num_local, tile, num_tokens, route)
¶
Thread r (r < 8 b): route r's permuted row, or -1 for another rank's expert.
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
_compare_exchange(c, a, b)
¶
_load_row(address)
¶
A lane's 8 consecutive FP32 at the 16-byte aligned address: two
16-byte loads, kept in program order around the PDL wait.
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
_sort_word(value, j)
¶
A word that orders as value (non-NaN), then the lower index j:
the order-preserving unsigned key of the value in bits 3..34, 7 - j in
bits 0..2. -0.0 takes the key of +0.0, as the two compare equal; the key of
any non-NaN value (-inf included) is above 0, the word of a popped slot.
Integer operations only, so subnormals keep their order.
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
compile_routing(metadata, renormalize, options='')
¶
cute.compile the routing kernel of one variant, with these extra
compile options. Call the result with the tensors of route
(meta None without metadata), then scale, local offset, local count and
tile; it launches on the current stream.
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
compiled_routing(metadata, renormalize)
cached
¶
compile_routing of one variant, once per process (before CUDA graph
capture).
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
metadata_size(tile_n)
¶
int32 elements of the metadata for GEMM tile tile_n: the fields
above and the permuted-to-token map (MAX_CTAS CTAs of tile_n rows), plus a
guard element.
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
prepare(renormalize=True)
¶
Compile the variants route takes with and without metadata (before
CUDA graph capture).
Source code in vllm/models/muse_spark/nvidia/specialized_decode/cutedsl/moe/routing.py
route(logits, bias, ids, weights, scale, renormalize=True, metadata=None, local_expert_offset=0, num_local_experts=0, tile_n=0)
¶
ids [b, 8] (global expert ids) and weights [b, 8] of the top-8
of sigmoid(logits) + bias for FP32 logits [b, 256] (1 <= b <= 8, unit
column stride, 16-byte aligned rows) and bias (contiguous, 16-byte
aligned FP32 [256]), on the current stream of the logits' CUDA device (the
compiled call switches to it and back). With metadata (a contiguous,
16-byte aligned int32 vector of at least metadata_size(tile_n)
elements, aliasing neither ids nor weights), also the routing metadata of
the local experts [local_expert_offset, local_expert_offset +
num_local_experts) for GEMM tile tile_n (1 to 256), at the
META_* offsets.
Raises ValueError on arguments outside that contract (some through the
compiled call's own checks: dtypes, shapes, strides, alignment, devices).
Allocates nothing; graph-capturable once prepare compiled the variant.